Several different logic families have been developed for circuit design, each having various advantages and disadvantages relative to each other. Two of the more popular logic families are complementary metal oxide semiconductor (CMOS) and current mode logic (CML) (also known as emitter coupled logic—ECL). These logic families operate with different voltage levels. In many applications, it is necessary or desirable to provide an interface between an output signal of a first circuit, operating with CMOS devices and voltage levels, and an input of a second circuit, operating with CML circuits and voltage levels. In that case, a buffer is used between the first circuit and the second circuit which can translate the voltage levels of the output signal of the first CMOS circuit to appropriate voltage levels for the second, CML, circuit. Typically, the input stage of the second, CML, circuit will have a very high impedance such that the buffer is not required to support high current levels.
FIG. 1 shows one buffer 100 for interfacing complementary input signals having CMOS voltage levels to a circuit operating with CML voltage levels. Buffer 100 includes a first branch 110, a second branch 150, and a voltage-swing adjusting transistor 190. First branch 110 includes a first PMOS transistor 120 and a first NMOS transistor 130 connected in series. Second branch 150 includes a second PMOS transistor 170 and a second NMOS transistor 180 connected in series.
First branch 110 and second branch 150 are each connected between a first supply voltage VDD and the voltage-swing adjusting transistor 190. The voltage-swing adjusting transistor 190 in turn is connected between the first and second branches 110, 150, and a second supply voltage VSS. The first supply voltage VDD is supplied to the control terminal of voltage-swing adjusting transistor 190 to bias it in a linear operating range. Each of the first and second branches 110 and 150 receives one of a pair of complementary input signals, VIN and VIN(BAR), and outputs one of a pair of complementary output voltages VOUT(BAR) and VOUT. The control terminal of first PMOS transistor 120 is connected to VSS, and the control terminal of first NMOS transistor 130 receives VIN. The control terminal of second PMOS transistor 170 is connected to VSS, and the control terminal of second NMOS transistor 180 receives VIN(BAR).
Operationally, when VIN is a high voltage level (e.g., logical “1”) and VIN(BAR) is a low voltage level (e.g., logical “0”), then first NMOS transistor 130 is turned on and second NMOS transistor 180 is turned off. At the same time, first PMOS transistor 120 operates in an active region, and second PMOS transistor 170 is turned on. In that case, the output voltage VOUT(BAR) of first branch 110 is determined by the ratio of the resistances of first PMOS transistor 120 and voltage-swing adjusting transistor 190 as follows:VOUT(BAR)=VLOW=(VDD−VSS)*(R190/(R120+R190))  (1)where R120 is the resistance of first PMOS transistor 120, and R190 is the resistance of voltage-swing adjusting transistor 190. Equation (1) assumes that R130<<R190, and R130 <<R120, which will in general be true when VIN is a high voltage level (e.g., logical “1”) and VIN(BAR) is a low voltage level (e.g., logical “0”).
Meanwhile, the output voltage VOUT of second branch 150 is pulled up by second PMOS transistor 170 to be about equal to VDD.
On the other hand, when VIN is a low voltage level (e.g., logical “0”) and VIN(BAR) is a high voltage level (e.g., logical “1”), then the situation with respect to first and second branches 110 and 150 is reversed, such that VOUT(BAR) of first branch 110 is pulled up by first PMOS transistor 120 to be about equal to VDD, and:VOUT=VLOW=(VDD−VSS)*(R190/(R170+R190))  (2)where R170 is the resistance of second PMOS transistor 170. Equation (2) assumes that R180<<R190, and R180<<R170, which will in general be true when VIN is a low voltage level (e.g., logical “0”) and VIN(BAR) is a high voltage level (e.g., logical “1”).
So by proper selection of the channel widths of first PMOS transistor 120, second PMOS transistor 170, and voltage-swing adjusting transistor 190, it is possible to adjust the lower output voltage, VLOW, to a desired value between VSS and VDD. Therefore, the voltage swing by the complementary output signals VOUT and VOUT(BAR), to VLOW to VDD, can be adjusted to match the required voltage levels of a subsequent circuit operating with a different logic family, such as CML.
However, buffer 100 does one at least one serious disadvantage. In particular, voltage-swing adjusting transistor 190 is always biased “on” in the active region regardless of the states of the complementary input voltages VIN and VIN(BAR). Therefore, buffer 100 consumes more power than a “regular” CMOS buffer.
Therefore, there is also a need for a CMOS-like complementary buffer whose output voltage has a reduced swing, from VLOW to VDD, where VLOW>Vss. There is also a need for such a buffer where VLOW is adjustable. There is further a need for a buffer for interfacing complementary input signals having CMOS voltage levels to a circuit operating with CML voltage levels which can operate with reduced current/power consumption. There is still further a need for such a buffer which can achieve fast rise/fall times, and can make the rise and fall times to be about symmetrical.
In accordance with an example embodiment, a buffer for interfacing complementary input signals having complementary metal oxide semiconductor (CMOS) voltage levels to a circuit operating with current mode logic (CML) voltage levels, comprises: a first branch receiving a first one of the complementary input signals and outputting a first complementary output signal having CML voltage levels, and a second branch receiving a second one of the complementary input signals and outputting a second complementary output signal having CML voltage levels. The first branch includes:a first PMOS transistor having a first terminal connected to a first CMOS supply voltage, a second terminal providing the first complementary output signal, and a control terminal receiving the first complementary input signal; and a first NMOS transistor and a second PMOS transistor connected in series between the second terminal of the first PMOS transistor and a second CMOS supply voltage. The first NMOS transistor has a control terminal receiving the first complementary input signal, and the second PMOS transistor has a control terminal receiving a first branch bias voltage. The second branch includes: a third PMOS transistor having a first terminal connected to the first CMOS supply voltage, a second terminal providing the second complementary output signal, and a control terminal receiving the second complementary input signal; and a second NMOS transistor and a fourth PMOS transistor connected in series between the second terminal of the third PMOS transistor and the second CMOS supply voltage. The second NMOS transistor has a control terminal receiving the second complementary input signal, and the fourth PMOS transistor has a control terminal receiving a second branch bias voltage.
In accordance with another example embodiment, a buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes a first branch outputting a first complementary output signal and a second branch outputting a first complementary output signal. The first branch comprises a first PMOS transistor and a first NMOS transistor connected in series with a first voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the first PMOS sand NMOS transistors of the first branch each receive a first one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the first complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region. When the first complementary input signal has a second voltage level, then current through the first voltage-swing adjusting transistor is shut-off by one of the first PMOS and NMOS transistors of the first branch. The second branch comprises a second PMOS transistor and a second NMOS transistor connected in series with a second voltage-swing adjusting transistor between the first supply voltage and the second supply voltage. Control terminals of the second PMOPS and NMOS transistors of the second branch each receive a second one of the complementary input signals, and a control terminal of the second voltage-swing adjusting transistor receives a second bias voltage. When the second complementary input signal has the first voltage level, the second voltage-swing adjusting transistor operates in the linear region. When the second complementary input signal has the second voltage level, then current through the second voltage-swing adjusting transistor device is shut-off by one of the transistors of the second branch.